Processor Types (Cambridge (CIE) A Level Computer Science): Revision Note
Exam code: 9618
RISC & CISC
A computer processor will have an instruction set that it can use to execute programs
This will vary from one processor to the next
There are 2 types of processors:
Reduced Instruction Set Computer (RISC)
Complex Instruction Set Computer (CISC)
RISC
Reduced Instruction Set Computer (RISC) consists of a smaller instruction set with more simple instructions
Each instruction takes one clock cycle to execute which makes it more suitable for pipelining
Compilers are more complicated so will generate more instructions
Has fewer addressing modes
Is usually used in smartphones and tablets
CISC
Complex Instruction Set Computer (CISC) consists of a larger instruction set which includes more complex instructions
As the instructions are more complex, they can take more than one clock cycle to execute
Has more general purpose registers
Instructions take up less space in memory
Is usually used in laptops and desktop computers
What’s the difference between RISC & CISC?
|
|
|
|---|---|---|
Feature | Has fewer transistors | Has more transistors |
Takes one clock cycle per instruction | Takes multiple clock cycles per instruction | |
Suited to pipelining | Not suited to pipelining | |
Compilers are more complicated | Compilers are less complicated | |
Has fewer general purpose registers | Has more general purpose registers | |
Used in smartphones and tablets | Used in laptops and desktops | |
Has fewer addressing modes | Has more addressing modes | |
Benefits / Drawbacks | Requires less power | Requires more power |
Costs less to manufacture | Costs more to manufacture | |
Takes up more space in memory | Takes up less space in memory |
A program that has been written for a RISC processor won’t work on a CISC processor and vice versa
A program that has been written for a RISC processor won’t necessarily work on another RISC processor as they may have different instruction sets
Interrupt handling on RISC & CISC
The concept of interrupt handling is covered in section 4, interrupts
Feature | CISC | RISC |
|---|---|---|
Instruction complexity | CISC has complex instructions, often with built-in support for interrupt routines | RISC has simple, fixed-length instructions, interrupt handling done using simpler routines |
Interrupt handling | Often uses microcode and dedicated hardware instructions to manage interrupts efficiently | Uses software-based interrupt handlers, managed through general-purpose registers and simple instructions |
Context switching | May have hardware support to save and restore processor state automatically | Typically handled in software, giving more control but requiring more instructions |
Speed of response | Generally faster interrupt handling due to built-in support | Slower, but more flexible and consistent across all instructions |
Instruction cycle impact | CISC can handle multiple tasks in a single instruction, including context saving | RISC uses multiple simple instructions, giving the OS greater control |
CISC processors often have dedicated instructions for handling interrupts, making the process more efficient but less flexible
RISC processors rely more on software routines, making interrupt handling slightly slower, but simpler and more predictable
Both architectures aim to respond to interrupts quickly and resume execution correctly, but they do so using different design philosophies
Worked Example
Reduced Instruction Set Computers (RISC) and Complex Instruction Set Computers (CISC) are two types of processor.
Tick (3) one box in each row to show if the statement applies to RISC or CISC processors.[2]
Statement | RISC | CISC |
|---|---|---|
uses a smaller instruction set | ||
uses single-cycle instructions and limited addressing modes | ||
uses fewer general-purpose registers | ||
uses both hardwired and micro-coded control unit | ||
uses a system where cache is split between data and instructions |
Answer
Statement | RISC | CISC |
|---|---|---|
uses a smaller instruction set | ✓ | |
uses single-cycle instructions and limited addressing modes | ✓ | |
uses fewer general-purpose registers | ✓ | |
uses both hardwired and micro-coded control unit | ✓ | |
uses a system where cache is split between data and instructions | ✓ |
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