1.1 Structure & Function of the Processor (OCR A Level Computer Science) Flashcards
Exam code: H446
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Define register.
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Cards in this collection (44)
Define register.
A register is a temporary storage location inside the CPU used for a single specific purpose, with faster access than RAM.
True or False?
The address bus is bidirectional and transfers both addresses and data.
False.
The address bus is unidirectional (CPU → memory/I/O) and only transfers memory addresses.
The is responsible for decoding instructions and controlling how data moves within the CPU.
The Control Unit is responsible for decoding instructions and controlling how data moves within the CPU.
What is the main function of the ALU in the CPU?
The Arithmetic and Logic Unit (ALU) performs arithmetic calculations and logic comparisons within the CPU.
The bus transfers data and instructions between the CPU, memory, and I/O devices, and is .
The data bus transfers data and instructions between the CPU, memory, and I/O devices, and is bidirectional.
Define internal bus.
An internal bus is a communication pathway within the CPU that transfers data between its components such as registers, ALU, and cache.
Define fetch-decode-execute cycle.
The fetch-decode-execute cycle is the process that the CPU repeatedly goes through to process instructions by fetching, decoding, and executing them.
What are the three main stages of the fetch-decode-execute cycle?
The three main stages are fetching, decoding and executing.
During the fetch stage, the value from the PC is copied to the , and the data from that location in memory is sent to the MDR.
During the fetch stage, the value from the PC is copied to the MAR, and the data from that location in memory is sent to the MDR.
Which register is responsible for holding the address of the next instruction to be fetched?
The Program Counter (PC) holds the address of the next instruction to be fetched.
The stores the value currently being worked on during arithmetic operations, such as addition or subtraction.
The ACC (Accumulator) stores the value currently being worked on during arithmetic operations, such as addition or subtraction.
Define opcode.
An opcode is the part of an instruction that specifies the operation to be performed by the CPU.
True or False?
The value from the MDR is sent to the CIR during the decode stage.
True.
During the decode stage, the data is sent from the MDR to the CIR.
When executing the instruction STA count, if the accumulator contains 9 and count is memory location 16, what are the values stored in the MDR and MAR?
The MDR will hold the value 9, and the MAR will hold 16.
Define clock speed.
Clock speed is a measure of how many state changes the CPU performs per second, usually measured in Hertz (Hz).
True or False?
A CPU with a higher clock speed can execute more instructions per second.
True.
A higher clock speed means the CPU can perform more fetch-decode-execute cycles per second, allowing it to execute more instructions in the same time.
A core is a unit within the CPU that can process instructions independently.
A core is a processing unit within the CPU that can process instructions independently.
What is parallel processing in the context of CPUs?
Parallel processing is when multiple CPU cores work simultaneously on different tasks, increasing the speed at which a computer can perform operations.
Define cache in a CPU.
Cache is a part of primary storage that stores frequently used data and instructions close to the CPU for quick access.
The more there is in a CPU, the more data can be stored for quick access, speeding up performance.
The more cache there is in a CPU, the more data can be stored for quick access, speeding up performance.
What is the purpose of different levels of cache (L1, L2, L3) in a CPU?
Different levels of cache (L1, L2, L3) provide varying sizes and speeds of memory, with L1 being the fastest and smallest, to efficiently store and access data used by the CPU.
A dual core processor is not always as fast as a single core processor because some tasks cannot be split between cores.
A dual core processor is not always twice as fast as a single core processor because some tasks cannot be split between cores.
Define pipelining.
Pipelining is the process of carrying out multiple instructions concurrently by having each instruction at a different stage of the fetch-decode-execute cycle.
What happens to the pipeline in the case of a branch instruction?
In the case of a branch, the pipeline is flushed, meaning instructions in the pipeline are discarded to handle the change in flow.
Why does pipelining improve processor performance?
Pipelining reduces latency and increases the speed of execution because the CPU is not idle while waiting for the next instruction; all parts of the processor can be used at any instance in time.
In pipelining, one instruction can be while the previous one is being and the one before is being .
In pipelining, one instruction can be fetched while the previous one is being decoded and the one before is being executed.
True or False?
Pipelining allows all parts of the processor to be used at any moment in time.
True.
Pipelining enables concurrent processing of instructions at different stages, meaning all parts of the processor can be in use simultaneously.
What is the fetch-decode-execute cycle?
The fetch-decode-execute cycle is the process where the CPU fetches an instruction, decodes it, then executes it, repeatedly, to run programs.
Pipelining the CPU from being idle while waiting for the next instruction, which the speed of execution.
Pipelining prevents the CPU from being idle while waiting for the next instruction, which increases the speed of execution.
In pipelining, what are the three main stages that instructions move through?
The three main stages are fetch, decode, and execute.
Pipelining reduces and improves processor .
Pipelining reduces latency and improves processor performance.
Define computer architecture.
A computer architecture describes how a computer uses components and instructions to function as a system.
Define Von Neumann architecture.
The Von Neumann architecture is a computer architecture where data and instructions are stored together in a single memory and use a single set of buses for communication.
Define Harvard architecture.
The Harvard architecture is a computer architecture with separate memory units and buses for instructions and data, allowing concurrent access and improved performance.
What is the main difference in memory organisation between Von Neumann and Harvard architectures?
Von Neumann architecture uses a unified memory for both instructions and data, while Harvard architecture separates instruction and data memory.
True or False?
Harvard architecture uses a single bus for both instructions and data.
False.
Harvard architecture uses separate buses for instructions and data, allowing them to be accessed concurrently.
In Harvard architecture, the system has memory units for storing and .
In Harvard architecture, the system has separate memory units for storing data and instructions.
In Von Neumann architecture, and are stored together in a memory.
In Von Neumann architecture, data and instructions are stored together in a single memory.
What are the three types of buses in Von Neumann architecture?
The three types of buses are the data bus, address bus, and control bus.
What is the function of the Control Unit (CU) in both Von Neumann and Harvard architectures?
The Control Unit (CU) retrieves, decodes, and executes instructions, and coordinates the activities of other units in the computer.
What operations does the Arithmetic Logic Unit (ALU) perform in computer architectures?
The Arithmetic Logic Unit (ALU) carries out arithmetic and logic operations such as addition, subtraction, multiplication, division, and comparisons.
Define special register in Von Neumann architecture.
A special register is a storage location within the CPU used to hold data, instructions, or addresses temporarily during processing.
How does having separate buses for instructions and data improve performance in Harvard architecture?
Separate buses allow instructions and data to be accessed concurrently, speeding up overall system performance.
True or False?
Harvard architecture allows pipelining because data and instructions can be fetched at the same time.
True.
With separate instruction and data buses, pipelining is possible because the next instruction can be fetched while the current one is being executed.
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