Pipelining (OCR A Level Computer Science): Revision Note
Exam code: H446
Pipelining
What is pipelining?
In A Level Computer Science, pipelining is the process of carrying out multiple instructions concurrently
Each instruction will be at a different stage of the fetch-decode-execute cycle
One instruction can be fetched while the previous one is being decoded and the one before is being executed
This table shows which stage each instruction is at during each step:
|
|
|
|
|---|---|---|---|
Step 1 | Instruction A |
|
|
Step 2 | Instruction B | Instruction A |
|
Step 3 | Instruction C | Instruction B | Instruction A |
Step 4 | Instruction D | Instruction C | Instruction B |
While one instruction is being executed, the next instruction will be decoded and the following instruction will be fetched
How does pipelining improve processor performance?
Pipelining increases instruction throughput by overlapping stages, while latency per instruction remains unchanged
The CPU is not idle while waiting for the next instruction which increases the speed of execution
The next instruction is fetched while the current one is decoded/executed
All parts of the processor can be used at any instant in time
What happens to the pipeline when a branch is taken?
Pipelining works best when instructions run in sequence, because the next instructions are fetched before the current one has been executed
If a branch instruction is executed and the branch is taken, the instructions already fetched and decoded behind it are the wrong ones
These instructions are discarded: the pipeline is flushed
The processor then fetches from the new address in the PC, so the pipeline has to refill and some stages sit idle
This table shows instruction A as a branch to instruction X:
Fetch | Decode | Execute | |
|---|---|---|---|
Step 1 | Instruction A | ||
Step 2 | Instruction B | Instruction A | |
Step 3 | Instruction C | Instruction B | Instruction A (branch to X) |
Step 4 | Instruction X | ||
Step 5 | Instruction Y | Instruction X | |
Step 6 | Instruction Z | Instruction Y | Instruction X |
Instructions B and C are flushed, so no instruction is executed in steps 4 and 5
Programs with many branches therefore gain less from pipelining than programs that run mostly in sequence
Examiner Tips and Tricks
In an extended "discuss pipelining" question, the top band needs evaluation as well as description. Explain that branches flush the pipeline, so the benefit depends on how much of the program runs in sequence.
Do not confuse pipelining with multiple cores. Pipelining overlaps the stages of the FDE cycle inside one processor.
Unlock more, it's free!
Was this revision note helpful?
Build on this topic