Exam code: H446
A charity uses a desktop computer to record financial donations that it receives. The computer contains a single core, 2.4GHz processor with 2MB cache.
The processor contains registers including the accumulator and the program counter. The contents of these registers are modified during the Fetch-Decode-Execute cycle.
State the name of three other registers that are used during the Fetch-Decode-Execute cycle.
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A program written using the Little Man Computer instruction set is shown in Fig. 1.
Various registers are used when the program above is executed.
State what is meant by the term ‘register’.
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OCR Insurance uses a computer system to calculate the price that customers pay for car insurance.
The computer system contains a CPU, GPU, RAM and ROM
State two factors that affect the performance of a CPU.
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A charity uses a desktop computer to record financial donations that it receives. The computer contains a single core, 2.4GHz processor with 2MB cache.
The processor uses the Von Neumann architecture.
Give one way that the Harvard architecture differs from the Von Neumann architecture.
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A charity uses a desktop computer to record financial donations that it receives. The computer contains a single core, 2.4GHz processor with 2MB cache
The processor contains registers including the accumulator and the program counter. The contents of these registers are modified during the Fetch-Decode-Execute cycle.
Describe how the accumulator is used during the Fetch-Decode-Execute cycle.
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The processor contains registers including the accumulator and the program counter. The contents of these registers are modified during the Fetch-Decode-Execute cycle.
Describe how the program counter is used during the Fetch-Decode-Execute cycle.
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The stored program concept uses the Fetch-Decode-Execute cycle to get the next instruction from memory and then execute it.
One of the instructions that may be fetched and executed as part of this cycle is a branch instruction.
State the name of the register that would be altered in the execute phase during a branch instruction.
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Fig. 1 shows assembly code written using the Little Man Computer (LMC).
The program calculates and outputs the total amount that is donated to a charity in any particular day. Depending on the amount, an additional bonus may be added to each amount donated.
This program is run on a processor that allows pipelining.
Define the term ‘pipelining’.
Explain one benefit to the charity of using a processor that allows pipelining.
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The CPU uses pipelining to improve efficiency.
Explain what is meant by the term ‘pipelining’
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Explain why pipelining can improve the performance of the processor.
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A program written using the Little Man Computer instruction set is shown in Fig. 1
Various registers are used when the program above is executed.
Explain how the accumulator is used when the line BRP pos is executed.
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A charity uses a desktop computer to record financial donations that it receives. The computer contains a single core, 2.4GHz processor with 2MB cache.
The processor uses the Von Neumann architecture.
Describe what is meant by the term ‘Von Neumann architecture’.
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A charity is concerned that the performance of their computer is not sufficient and wishes to replace the processor.
Give two features of a replacement processor that would increase the typical performance of the computer.
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The stored program concept uses the Fetch-Decode-Execute cycle to get the next instruction from memory and then execute it.
Describe what happens during the fetch stage of the Fetch-Decode-Execute cycle.
You should state the different registers and buses that are used in your answer.
Three ways of improving the performance of a CPU are increasing the clock speed, adding more cores and using pipelining.
Explain how pipelining improves the performance of a CPU.
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A company is designing a real-time audio processing system used during live performances.
The system must process continuous streams of data with minimal latency while repeatedly fetching instructions.
Evaluate whether a Von Neumann architecture or a Harvard architecture would be more suitable for this system
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A graphics rendering system uses a pipelined processor to improve performance. However, the rendering code contains frequent conditional branch instructions.
Explain why the presence of these branch instructions may prevent the processor from achieving its theoretical maximum performance, even though pipelining is used.
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A processor uses a deep instruction pipeline to improve performance.
The program being executed contains a high frequency of conditional branch instructions.
Explain why increasing the depth of the pipeline may result in diminishing performance gains when running this program.
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A processor is executing instructions from main memory using the Fetch–Decode–Execute cycle. During execution, a delay occurs when accessing memory.
Explain how the fetch stage of the Fetch–Decode–Execute cycle contributes to this delay.
You should refer to registers and buses.
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A program includes multiple branch instructions that alter the normal execution sequence.
Explain how the Fetch–Decode–Execute cycle ensures the correct instruction is fetched next, even when program flow changes.
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A pipelined processor is executing a program containing frequent branch instructions.
Explain how these branch instructions can reduce the efficiency of pipelining.
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An embedded system used in high-speed industrial robotics currently utilises a single-core processor with a clock speed of 2.0 GHz. The manufacturer plans to upgrade the processor to a 4.0 GHz model to handle more complex real-time sensory data.
Evaluate the extent to which doubling the clock speed will improve the instruction throughput of this system. In your answer, you should discuss the impact on the system clock and identify two other hardware factors that could prevent the system from achieving a linear performance increase.
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A processor executes arithmetic instructions where the result of one instruction is required by the next instruction immediately.
Explain how the interaction between registers and the Arithmetic Logic Unit (ALU) helps minimise performance delays in this situation.
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