Central Processing Unit (CPU) Architecture (Cambridge (CIE) A Level Computer Science): Flashcards

It stores a value that can be added to an address to get the effective memory address, and is used for indexed addressing.

It stores flags that reflect the outcome of CPU operations, holding individual bits that are set or cleared depending on the result of an instruction, such as overflow.

The acronym CIR stands for the Current Instruction Register.

The name of the register, its acronym, and the purpose of the register.

False.

The MAR holds the address of where data is to be fetched from; it is the MDR that stores the data or instruction fetched.

Processing all data within the computer.

The Arithmetic Logic Unit (ALU), the Control Unit (CU), the system clock, the Immediate Access Store (IAS) and the buses.

It performs calculations, such as add and subtract, and logic operations, such as AND and OR.

It manages and controls the execution of instructions and directs data flow.

It sends out regular pulses to synchronise all CPU operations.

The main memory where instructions and data needed by the CPU are temporarily stored.

A bus is a set of parallel wires through which data or signals are transmitted from one component to another.

The address bus, the data bus and the control bus.

It carries location data (addresses) that data is written to or read from, and it is unidirectional.

It carries data or instructions, and it is bidirectional.

The control bus carries commands and control signals, and is bidirectional.

False.

The address bus is unidirectional; the data and control buses are the bidirectional ones.

A core acts like a mini CPU that can fetch, decode and execute instructions on its own.

Its own Control Unit, Arithmetic Logic Unit and registers.

Parallel processing, where multiple instructions are processed at the same time.

4 cores × 3 billion gives 12 billion instructions per second.

Some time is used for organising tasks between cores, and not all tasks can be split across cores because some are sequential and must be done step-by-step.

The clock controls the timing of operations inside the CPU, constantly switching between 0 and 1; each switch is a state change, which can represent one step in the fetch-decode-execute cycle.

It measures how many state changes happen per second, where 1 cycle per second = 1 Hz.

A typical clock speed of 2.3 GHz means 2.3 billion cycles per second.

The CPU can execute more instructions per second, helping the computer run tasks more quickly and efficiently.

Cache is part of primary storage that stores frequently used data and instructions, located closer to the CPU than RAM so it is faster to access.

More data is stored nearby, which means less time waiting for data from RAM.

Inside each CPU core; it is the fastest and the smallest.

It is shared by all cores, and is slower than L1 and L2 but the largest.

Bus width is the number of bits a bus can carry at once, so a wider bus can transfer more bits in a single operation.

Faster processing and more efficient memory access, which matters for high-performance tasks such as gaming, video editing and large data processing.

False.

A state change can represent one step in the cycle, but some instructions may take more than one cycle.

Universal Serial Bus — a serial communication method that operates asynchronously.

The physical shape and design of the connector.

Its small size, its transfer speeds, and its ability to carry power.

The generation of USB technology, which determines the speed and performance.

USB 2.0 reaches 480 Mbps, while USB4 and USB4 2.0 reach up to 80 Gbps.

The computer automatically detects the device, then looks for the correct driver — loading it if already installed, searching for a compatible one if the device is new, and requiring the user to install one manually if none is found.

Devices are automatically detected with drivers loaded, connectors fit in only one way which prevents incorrect connections, usage is standardised so support is widely available, several data transmission rates are supported, and newer standards are backwards compatible.

The maximum USB cable length is roughly 5 metres, which limits its use over long distances.

It is a digital port carrying both video and audio output, and it replaced older VGA analogue systems.

Widescreen format, higher resolution, faster refresh rates, and a wider colour range of millions of variations.

Up to 10 Gbps.

High-bandwidth Digital Content Protection — devices check for an authentication key before sending data, and if authenticated a handshake occurs, which helps prevent unauthorised copying of protected content.

640 × 480 pixels at up to 60 Hz, but only 16 colours at that rate.

By reducing the resolution — at 320 × 200 it can support up to 256 colours.

Lower image quality over long cables, and it is more likely to experience signal loss or interference.

False.

VGA was the standard for video output only and is an analogue signal; it is HDMI that carries both video and audio digitally.

The fetch-execute cycle is the process the CPU goes through repeatedly to process instructions.

Fetching an instruction from memory, decoding the instruction, and executing it.

The instruction is interpreted, and the required data is read and retrieved from their addresses.

The MAR, the Memory Address Register.

The address is sent via the address bus, and a read instruction is sent on the control bus.

It is sent down the data bus to the MDR.

During fetch the PC is incremented by 1, ready for the next instruction.

The opcode and the operand.

The instruction is sent from the CIR to the CU, which decodes what to do next.

RTN is a way of describing how data moves between registers in a CPU during the fetch-execute cycle, using symbols for registers and the ← arrow to show data being transferred.

[ ] means the contents of a register, while [[ ]] means the contents of the memory location addressed by that register.

MAR ← [PC], then MDR ← [[MAR]], then PC ← [PC] + 1, then CIR ← [MDR].

MAR ← [operand], then MDR ← [[MAR]], then ACC ← [MDR].

MAR ← [operand], then MDR ← [ACC], then [[MAR]] ← [MDR].

If [ACC] = 0 then PC ← [operand].

The value from RAM is loaded into the MDR, the calculation happens in the ALU, and the result is stored in the ACC.

False.

There is no specific register transfer in decode — the CU decodes the instruction held in the CIR.

An interrupt is a signal to the processor that stops its current task and performs a different task temporarily.

It suspends the current program execution and transfers control to an interrupt service routine.

Real-time event handling, such as hardware errors; device communication, such as printer jams and network errors; and multitasking, suspending one application so the user can switch to another.

Hardware interrupts, software interrupts and trap interrupts.

They are generated by external devices, such as keyboard input, mouse movements or disk I/O requests.

They are triggered by software or the operating system, such as an application request to open a file or a division by zero error.

One that is intentionally triggered by a program, for example during software debugging or when handling unexpected error cases.

Interrupt request (IRQ), interrupt acknowledge, ISR lookup, ISR execution and interrupt exit.

The interrupt handler decides if the interrupt needs to be dealt with now or later, and if so the current contents of the processor registers are saved in memory.

The processor restores the contents of the registers that were saved, and the fetch-decode-execute cycle is resumed.

An ISR is a special function that handles a particular interrupt type, and each type of interrupt has a corresponding routine.

Because ISRs often need to handle time-sensitive events, so they are designed to minimise the time taken to execute.

Because many things can go wrong at the same time, so the processor must be able to switch to resolving a higher-priority interrupt, with lower-priority ISRs temporarily suspended.

Nesting of interrupts refers to the processor's ability to handle interrupts within interrupts.

An interrupt flag is raised in the interrupt register, the system finishes its current fetch-execute cycle, the register is checked for a higher priority interrupt, the current register contents are pushed to the stack, the appropriate ISR is executed, then the register contents are restored and control returns to the original process.

False.

The system finishes its current fetch-execute cycle first, and only then checks the interrupt register.